1. Field of the Invention
The invention relates to a motherboard of a desktop computer and a memory device thereof and, more particularly, to a motherboard and a memory device which can process work at a higher frequency and enhance the system performance of a desktop computer in a unit interval.
2. Description of the Related Art
Generally speaking, the motherboard of a conventional desktop computer is usually provided with a memory slot for inserting a dual inline memory module (DIMM), which is a standard configuration established by the joint electron device engineering council (JEDEC) and commonly used by the motherboard of the conventional desktop computer.
The JEDEC establishes some reference design configuration for the unbuffered DIMM of the desktop computer. When memory chips on the unbuffered DIMM are double data rate two synchronous dynamic random access memory (DDR2 SDRAM), the JEDEC suggests using the T branch topology. When the memory chips on the unbuffered DIMM are double data rate three synchronous dynamic random access memory (DDR3 SDRAM), the JEDEC suggests using the fly-by bus topology.
FIG. 1 is a schematic diagram showing a conventional DIMM 100 using the T branch topology established by the JEDEC, and a terminator T is connected to a branch point A at the first layer. Theoretically, for the T branch topology established by the JEDEC, branch wires are completely symmetrical, and lengths of wires are balanced by bilateral symmetry. The branch wires are used to connect each of memory chips DDR2 SDRAM0 to DDR2 SDRAM7 on the unbuffered DIMM 100. Therefore, reflection effect of address line signals and command line signals sent out by a memory controller 101 is balanced off by each other to achieve the objective of not damaging the quality of the signals.
The address line signals and the command line signals sent out by the memory controller 101 are not delayed on their transmission path, and therefore, all the memory chips DDR2 SDRAM0 to DDR2 SDRAM7 can receive the address line signals and the command line signals sent out by the memory controller 101 at the same time. Then, the memory controller 101 can do read-write operation on the memory chips DDR2 SDRAM0 to DDR2 SDRAM7 at the same time to enhance the system performance of the desktop computer in a unit interval.
Under an actual condition, when the T branch topology established by the JEDEC is utilized to lay out the wires on a printed circuit board (PCB) for the unbuffered DIMM 100, branches are too much to obtain the completely symmetric branch wires and the wires with the balanced lengths. Then, the reflection effect of the address line signals and the command line signals sent out by the memory controller 101 cannot be balanced off by each other. Thus, the memory chips DDR2 SDRAM0 to DDR2 SDRAM7 receive the address line signals and command line signals which are deformed.
When the operation frequency of the unbuffered DIMM 100 is over a frequency range which is 533 MHz to 800 MHz and is established by the JEDEC, the address line signals and the command line signals sent out by the memory controller 101 may generate a resonant phenomenon. Then, the address line signals and the command line signals received by the memory chips DDR2 SDRAM0 to DDR2 SDRAM7 are seriously attenuated. The above deformed or attenuated signals are not wanted by designers in the computer industry.
FIG. 2 is a schematic diagram showing a conventional unbuffered DIMM 200 using the free-by bus topology established by the JEDEC. Theoretically, the signal transmission mode of the fly-by topology established by the JEDEC is illustrated as follows. A signal is transmitted from the memory chip DDR3 SDRAM0, and then it is transmitted to the memory chips DDR3 SDRAM1 to DDR3 SDRAM7 in series. Finally, a terminator T is connected to the end of the signal transmission path to prevent the address line signals and the command line signals sent out by the memory controller 201 from being reflected. Therefore, since the reflection effect is nearly nonexistent, the address line signals and the command line signals sent out by the memory controller 201 have preferred signal quality, and work at a higher frequency can be processed. The operation frequency established by the JEDEC is 800 MHz to 1600 MHz. Since the fly-by topology established by the JEDEC does not have many branches, the wiring mode of laying out the wires on the PCB is simple.
Under the fly-by bus topology established by the JEDEC, since the address line signals and the command line signals sent out by the memory controller 201 are transmitted from the memory chip DDR3 SDRAM0 to the memory chip DDR3 SDRAM7 in series, the transmitted signals are delayed. The memory chips DDR3 SDRAM0 to DDR3 SDRAM7 begin to work at different time after they receive the address line signals and the command line signals sent out by the memory controller 201, and therefore, the memory controller 201 has to wait for delay time before it does read-write operation on the memory chips DDR3 SDRAM0 to DDR3 SDRAM7. Therefore, the system performance of the desktop computer in a unit interval decreases.
Since the memory controller 201 has to wait for the delay time before it does the read-write operation on the memory chips DDR3 SDRAM0 to DDR3 SDRAM7, the memory controller 201 has to have the capability of independently controlling each of the memory chips DDR3 SDRAM0 to DDR3 SDRAM7 to finish the read-write operation. Therefore, the design of the memory controller 201 is relatively complex.